1 article(s) from Kallio, Pasi
Conceptual diagram of a SiNW FET.
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Typical measurement system.
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Shape of the power spectrum of IRS from 5-bit length shift register.
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Schematic of the applied SiNW FET device.
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SEM image of the SiNW FET device. The scale bar is 20 µm.
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Ids–Vds DC measurement results.
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Ids–Vg DC measurement results.
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Conceptual diagram of the measurement setup.
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Simplified schematic of the measurement amplifier.
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Generated excitation sequence; a) sample in the time domain, and b) (scaled) energy content.
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Admittance spectroscopy for gate voltages from 1.0 V to 3.0 V.
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Admittance spectroscopy for gate voltages of 2.0 V and 2.2 V.
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Beilstein J. Nanotechnol. 2014, 5, 964–972, doi:10.3762/bjnano.5.110
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