Metal oxide-graphene field-effect transistor: interface trap density extraction model

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship Ids–Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage Ctot–Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.


Introduction
Graphene has recently attracted a lot of attention. Its 2D nature along with its significantly high carrier mobility (≈15,000 cm 2 /(V·s)) make it an ideal material to replace silicon [1] in the more than Moore era. During deposition of the dielectric layer on graphene as well as from deposition of graphene on the substrate defects may be formed in the film resulting in the presence of trap states; D it states (cm −2 ·eV −1 ) at the interface between the dielectric layer and graphene channel [2,3]. These trap states trap mobile carriers degrading the gate field modulation effect, thereby resulting in degraded surface potential.
Popular metal-oxide-graphene field-effect transistor (MOGFET) models do not take into account the detrimental effect of D it states on device surface potential [4,5]. Zebrev et al. [6], recently presented a model that takes into account the effect of D it states on the device current. A similar approach has been used by [7]. However, Zebrev's drain current expression is based on the assumption of presence of constant D it states over the entire energy range of operation of the device. The assumption does not work generally; recently, significantly varying D it distribution has been reported for metal-oxide-graphene (MOG) capacitors [8]. This suggests the need for a model that can analytically calculate the interface trap density of MOGFET devices that could later be used in drain current I ds models for efficient I ds performance prediction.
This work presents a method to extract interface trap density of MOGFET with the help of device C tot -V gs data. Basic equations and parameters needed to extract interface trap density are explained below. Extraction and verification of extracted trap density is explained following the section below.

Basic equations and parameters
Basic equations Figure 1a shows the schematic of a typical MOGFET. The channel consists of monolayer graphene with length L deposited on a SiO 2 layer with a p-type doped silicon substrate as the backgate (only top-gated monolayer MOGFET is considered in this work). The gate stack consists of a dielectric layer with thickness t ox and a metal gate. Q it in Figure 1a refers to the interface trap charge found at the dielectric/channel interface. Figure 1b shows the equivalent capacitive circuit of the typical capacitances in the MOGFET device. In a MOGFET top gate capacitance C ox is in series with the parallel combination of interface trap capacitance C it which originates from the presence of D it states, and C q the quantum capacitance.
C q is a graphene material property and is given by [9], (1) where, q is the charge on an electron, φ s is surface potential, is the Planck's constant, v f is the fermi velocity (1 × 10 8 cm 2 /(V·s)), C qi is a fitting factor independent of φ s , and accounts for the finite C q observed at Dirac point (DP) (at which the fermi level E f = qφ s = 0 = E D , where E D is the energy (eV) at DP).
The total capacitance C tot of MOGFET is given by, Applying the capacitor divider relation to Figure 1b, the surface potential φ s of MOGFET is given by, where V gs is the gate voltage, V DP is the gate voltage at DP known to be caused by the gate-metal/graphene workfunction difference [10], and/or interface trap states [11], and V c is the channel voltage drop due to the applied drain bias V ds with V c = 0 at the source end and V c = V ds at the drain end.
Solving self-consistently for φ s in Equation 3 and C q = (β g qφ s ), φ s is given by Equation 4, Here, the positive (negative) sign applies when (V gs − V DP − V c ) C ox > 0 (< 0). The sum of C q + C it in Equation 2 and Equation 3 can be labeled as C x . The next few paragraphs explain the procedure for extraction of experimental φ s , C q , C it and Q it parameters of two sample MOGFET devices which are then used in extraction of their D it distributions explained in the section "Extraction of interface trap states".
Experimental φ s , C it , and Q it extraction Surface potential φ s and C it were extracted for two MOGFET devices using experimental C tot -V gs data (from herein referred as C tot_exp ) taken from Device 1 [7], and device 2 [12] (with back-gate bias = 0 V, and V ds = 0). The extracted φ s and C it parameters obtained using experimental C tot_exp data will be referred to as φ s_exp and C it_exp . The device parameters for both the devices are mentioned in Table 1.
As mentioned in [12] for Device 2, the DC method used to find C ox involves a large amount of ambiguity due to imprecise evaluation of the back-gate capacitance [13], and consequently C ox . A C ox value of 1.00 μF/cm 2 along with available C q and C it parameters from [12] in Equation 2 was found to reproduce available C tot_exp , and C q results very well, instead of the reported value of 0.76 μF/cm 2 , the former is used instead in this work. The extraction procedure is described next. C x can be found from Equation 5 which is derived from manipulating Equation 2. Here C tot is the respective experimental C tot -V gs data for the two experimental devices and C ox is their oxide capacitances mentioned in Table 1.
(5) C x obtained from the above equation is then substituted in Equation 3 to extract device's φ s as a function of V gs , with all the other parameters in Equation 3 known. The extracted φ s is referred to as φ s_exp as device's surface potential extracted from experimental C tot -V gs data.
Once φ s_exp is obtained, C q can be calculated from Equation 1. Finally, device's C it can be obtained using the expression below. The extracted C it is referred to as C it_exp as device's interface trap capacitance obtained from experimental C tot -V gs data.
By substituting C it_exp in the expression given below, device's Q it can be extracted.
In Equation 7 E f = φ s_exp . The extracted Q it is referred to as Q it_exp as the interface trap charge extracted from experimental C tot -V gs data.
The relationship between C it and Q it is given by (8)

Extraction of interface trap states
For the extraction, according to standard convention [6] acceptor and donor type traps states were considered for the n-type MOGFET, and p-type MOGFET operation, respectively.
The interface trap charge for both acceptor type and donor type trap states can be calculated from the following [11], (10) Here, in Equation 9-11, Q it_calc denotes the calculated interface trap charge, F tA (F tD ) denotes the probability of occupation of k acceptor (donor) type trap states, and E tA (E tD ) denotes the ith energy level of each of these k acceptor (donor) type trap state. D it is the interface trap density defined at the ith energy level. Q it can be found by the integral of product of all the k trap states with their respective F tA (F tD ) between E D and E f . If Q it_exp and Q it_calc values as a function of φ s_exp match it means the fitted D it values used in Equation 9 to calculate Q it_calc were a good fit to reproduce the extracted experimental Q it_exp . This step enables us to calculate D it values.
At this point, we have only calculated Q it_calc as a function of φ s_exp . In order to compare parameters consistently we need to self-consistently find Q it_calc as a function of φ s_calc , where φ s_calc refers to φ s calculated from Equation 4 using C it_calc as the input variable. C it_calc refers to C it calculated from Equation 8 using Q it_calc and φ s_calc as input variables. The selfconsistent C it_calc -φ s_calc calculation procedure is based on our earlier works on MOSFET interface trap drain current modeling [14,15]. The procedure is highlighted in Figure 3 and is described next.
The first step is calculating C it_calc from Equation 8 by substituting Q it_calc obtained in the previous step (i.e., during the D it extraction procedure) and the earlier obtained φ s_exp . The calculated C it is referred to as C it_calc . Calcuted C it_calc is then substituted in Equation 4 to find φ s_calc . This φ s_calc is then substituted back in Equation 9-11 using the already extracted interface trap distribution to calculate Q it_calc . This Q it_calc along with φ s_calc obtained in the previous step is substituted back in Equation 8 to find C it_calc which is then substituted in Equation 4 to find φ s_calc . This process is repeated back and forth until self-consistency is obtained between Q it_calc /C it_calc and φ s_calc . Now we can express Q it_calc /C it_calc as functions of φ s_calc , and in turn φ s_calc is calculated using C it_calc .
Interface trap distribution verification criteria simply implies that 1. Q it_calc (as a function of φ s_calc ) should match well with Q it_exp (as a function of φ s_exp ). 2. C it_calc (as a function of φ s_calc ) should match well with C it_exp (as a function of φ s_exp ). 3. φ s_calc should match well with φ s_exp .
If the respective calculated and experimental parameters are in reasonable agreement, it proves that the fitted D it values used to find the calculated parameters were reasonable (within a toler-ance limit) to match well the experimental parameters. The extracted D it distribution is shown in Figure 4; magenta for Device 1 and yellow for Device 2.

Results and Discussion
To prove the validity of the extraction criteria, the extracted experimental parameters, i.e., Q it_exp , C it_exp , φ s_exp , and C tot_exp are compared with the respective calculated, i.e., Q it_calc , C it_calc , φ s_calc , and C tot_calc parameters obtained using the extracted D it distribution, as shown in the following.    Also shown is φ s -ideal, calculated from Equation 4 with C it = 0 (dashed line). The surface potential calculated with no C it = 0 compared with the surface potential calculated considering C it clearly indicates that with no C it included in the surface potential calculation the result will be an erroneously calculated surface potential. Such an erroneous surface potential if used in surface potential based drain current models will lead to unrealistic prediction of device current. Blue symbols in Figure 6a and 6b show the difference in φ s_exp and φ s_calc . As the graph shows, the difference between the two is minimal. The model ensures accurate, realistic calculation of device surface potential by taking into account degradation caused by trap states. This feature could be used to develop more realistic drain current models. Figure 7a and 7b show for Device 1 and 2 respectively, the extracted C it_exp (symbols) from Equation 6, as a function of φ s_exp compared with the C it_calc (solid line), as a function of φ s_calc ; C it_exp is in reasonable agreement with C it_calc . Figure 7b and 7d show difference in C it_exp and C it_calc as a function of V gs . The error in C it_calc although, higher than Q it_calc is still negligible. This is proven when we substitute C it_calc in Equation 4 to calculate φ s_calc (when self-consistency is obtained), φ s_calc matches very well with φ s_exp as shown earlier in Figure 6.  Finally, C tot_exp is compared with C tot_calc calculated using C q_calc from Equation 1, and C it_calc obtained above in Equation 2, this is shown in Figure 8a and 8b for Device 1 and 2 respectively; C tot_exp (symbols) is in excellent agreement with C tot_calc (solid line). All calculated parameters dependent on D it states, i.e., Q it_calc , C it_calc , φ s_calc and device C tot_calc are in excellent agreement with the respective extracted experimental parameters, thereby validating the extracted D it distribution.
It must be mentioned part of this work is based on our earlier work on MoS 2 transistor [14] as briefly mentioned earlier. However, in that work the interface trap density of MoS 2 tran- sistor was extrated by simply fitting the Q it parameter in the device's drain current (I ds ) model to fit experimental device's I ds with the calculated one from the model. Next, device's φ s was calculated from the model equation. This φ s was substituted in Equation 9-11 (also used in that work) to fit E tA/D and D it values to match Q it obtained earlier by fitting device's I ds . This D it distribution extraction procedure is the same in both works. However, in this work, instead of fitting Q it in a drain current expression, a thorough analytical framework has been developed, based on fundamental MOGFET device physics, to extract important experimental parameters including Q it , C it and φ s data from experimental C tot -V gs data as highlighted in the section "Experimental φ s , C it , and Q it extraction". Using these experimental parameters as a reference and the framework developed earlier [14,15] an analytical framework was presented to extract the interface trap distribution of MOGFET devices.
To date, to the best of our knowledge this is the only such work in the field. No thorough quantitative, experimental data yet exists on interface trap distribution of graphene transistors. In light of this, this work will be a useful addition to graphenetransistor compact modeling literature.

Conclusion
In summary, a simple analytic method was introduced to extract the interface trap distribution of MOGFET devices using device's C tot -V gs data. The model makes use of the basic set of equations used to define device physics of MOGFET devices. Using the procedure mentioned above, interface trap densities of two reference experimental devices were extracted. Device parameters dependent on the extracted interface distribution including the calculated surface potential, interface trap charge, interface trap capacitance and total capacitance matched very well with the respective extracted experimental device parame-ters. The model enables calculation of device surface potential with the adverse effect of trap charge on device surface potential included. This capability could further be explored in surface potential based MOGFET I ds models to help predict MOGFET I ds -V gs performance more accurately by including the effect of interface trap charge on device surface potential.