1 article(s) from Garvey, Shane
Schematic depicting MLD processing applied to silicon on insulator wafers. It shows monolayer forma...
Jump to Figure 1
Electrochemical capacitance–voltage profile showing the impact of applying a SiO2 capping layer for...
Jump to Figure 2
AFM images of (a) as received SOI (b) SOI after MLD processing.
Jump to Figure 3
ECV plot of active carrier concentrations in a 66 nm SOI after MLD using a 50 nm sputtered SiO2 cap...
Jump to Figure 4
ECV plot of active carrier concentrations using bulk silicon samples to analyse the variation of th...
Jump to Figure 5
X-ray photoelectron spectroscopy (XPS) study showing that there is a degree of surface oxidation af...
Jump to Figure 6
Secondary ion mass spectrometry analysis of a P-MLD-doped 66 nm silicon on insulator substrate. Blu...
Jump to Figure 7
Beilstein J. Nanotechnol. 2018, 9, 2106–2113, doi:10.3762/bjnano.9.199
Subscribe to our Latest Articles RSS Feed.
Register and get informed about new articles.
Follow the Beilstein-Institut