Phosphorus monolayer doping (MLD) of silicon on insulator (SOI) substrates

• Noel Kennedy,
• Ray Duffy,
• Luke Eaton,
• Dan O’Connell,
• Scott Monaghan,
• Shane Garvey,
• James Connolly,
• Chris Hatem,
• Justin D. Holmes and
• Brenda Long

Beilstein J. Nanotechnol. 2018, 9, 2106–2113, doi:10.3762/bjnano.9.199

• silicon layer). Bulk silicon transistors encounter difficulties when scaled below 20 nm due to SCE and significant leakage currents, which increase their power consumption. SOI and three-dimensional finFET structures are two means of device scaling that are currently being pursued by the electronics

• community. Planar, fully depleted SOI (FD-SOI) has been used to provide a more cost-effective scaling mechanism than FinFET alternatives. Although initial wafer cost is higher for SOI compared to bulk silicon, which is used in finFETs, the further masking and etching required for fin production is both

Electrical characterization of single nanometer-wide Si fins in dense arrays

• Steven Folkersma,
• Janusz Bogdanowicz,
• Andreas Schulze,
• Paola Favia,
• Dirch H. Petersen,
• Ole Hansen,
• Henrik H. Henrichsen,
• Peter F. Nielsen,
• Lior Shiv and
• Wilfried Vandervorst

Beilstein J. Nanotechnol. 2018, 9, 1863–1867, doi:10.3762/bjnano.9.178

• the technique, this opens the prospect for the use of μ4PP in electrical critical dimension metrology. Keywords: critical dimension metrology; electrical characterization; finFET; micro four-point probe; sheet resistance; Introduction The transition from planar to three-dimensional transistor

• architectures such as the fin field-effect transistor (finFET) [1] has raised the need for measuring the electrical properties of nanometer-wide conducting features [2]. Recently, it has been shown that the micro four-point probe (μ4pp) technique, which is commonly used for sheet resistance measurements on