A mid-infrared focusing grating coupler with a single circular arc element based on germanium on silicon

• Xiaojun Zhu,
• Shuai Li,
• Ang Sun,
• Yongquan Pan,
• Wen Liu,
• Yue Wu,
• Guoan Zhang and
• Yuechun Shi

Beilstein J. Nanotechnol. 2023, 14, 478–484, doi:10.3762/bjnano.14.38

• cover the wavelength of 6–15 μm. Hence, it is a suitable material for biosensors applications in the MIR band [6]. In recent years, researchers have verified the feasibility of Ge MIR waveguides on various substrate materials, such as germanium on silicon (Ge-on-Si), germanium on silicon-on-insulator

Double-layer symmetric gratings with bound states in the continuum for dual-band high-Q optical sensing

• Chaoying Shi,
• Jinhua Hu,
• Xiuhong Liu,
• Junfang Liang,
• Jijun Zhao,
• Haiyan Han and
• Qiaofen Zhu

Beilstein J. Nanotechnol. 2022, 13, 1408–1417, doi:10.3762/bjnano.13.116

• grating (HCG) structures in periodic subwavelengths [9][10]. Among them, HCG structures built on silicon-on-insulator (SOI) substrates establish a new platform for integrated optics as well as optical sensing [11][12] owing to its high reflectivity in bandwidth (>99%) and compatibility with the

Liquid crystal tunable claddings for polymer integrated optical waveguides

• José M. Otón,
• Manuel Caño-García,
• Fernando Gordo,
• Eva Otón,
• Morten A. Geday and
• Xabier Quintana

Beilstein J. Nanotechnol. 2019, 10, 2163–2170, doi:10.3762/bjnano.10.209

• material paves the way to the use of large wafers, well-known efficient microelectronic processes and remarkable cost savings. Silicon waveguides can be developed on silicon dioxide, resulting in silicon-on-insulator (SOI) wafer structures compatible to CMOS processes [5]. This opens the possibility of

Experimental study of an evanescent-field biosensor based on 1D photonic bandgap structures

• Jad Sabek,
• Francisco Javier Díaz-Fernández,
• Luis Torrijos-Morán,
• Zeneida Díaz-Betancor,
• Ángel Maquieira,
• María-José Bañuls,
• Elena Pinilla-Cienfuegos and
• Jaime García-Rupérez

Beilstein J. Nanotechnol. 2019, 10, 967–974, doi:10.3762/bjnano.10.97

• fabricated in a silicon-on-insulator (SOI) chip in our clean-room facilities (Figure 1). The created chip layout contains four groups of sensors, each one comprising four PBG structures where the width of the transversal elements has been swept between 80 and 140 nm (wi = 80, 100, 120 and 140 nm for each of

Bidirectional biomimetic flow sensing with antiparallel and curved artificial hair sensors

• Claudio Abels,
• Antonio Qualtieri,
• Toni Lober,
• Alessandro Mariotti,
• Lily D. Chambers,
• Massimo De Vittorio,
• William M. Megill and
• Francesco Rizzi

Beilstein J. Nanotechnol. 2019, 10, 32–46, doi:10.3762/bjnano.10.4

• stress-driven artificial hair sensor. The fabrication process is subdivided into the following main steps: Depositing functional material layers: The flow sensor is based on a silicon-on-insulator (SOI) substrate which is made up of a 400 μm silicon wafer, a 2 μm thick silicon dioxide (SiO2) insulation

Charged particle single nanometre manufacturing

• Philip D. Prewett,
• Cornelis W. Hagen,
• Claudia Lenk,
• Steve Lenk,
• Marcus Kaestner,
• Tzvetan Ivanov,
• Ahmad Ahmad,
• Ivo W. Rangelow,
• Xiaoqing Shi,
• Stuart A. Boden,
• Alex P. G. Robinson,
• Dongxu Yang,
• Sangeetha Hari,
• Marijke Scotuzzi and
• Ejaz Huq

Beilstein J. Nanotechnol. 2018, 9, 2855–2882, doi:10.3762/bjnano.9.266

• well [153]. The fabrication of the cantilevers uses a surface micromachining process in order to form sharp tips. Standard IC planar processing of silicon on insulator (SOI)-wafers is employed in combination with bulk micromachining to form the cantilever. Details about the fabrication process can be

Metal–dielectric hybrid nanoantennas for efficient frequency conversion at the anapole mode

• Valerio F. Gili,
• Lavinia Ghirardini,
• Davide Rocco,
• Giuseppe Marino,
• Ivan Favero,
• Iännis Roland,
• Giovanni Pellegrini,
• Lamberto Duò,
• Marco Finazzi,
• Luca Carletti,
• Andrea Locatelli,
• Aristide Lemaître,
• Dragomir Neshev,
• Costantino De Angelis,
• Giuseppe Leo and
• Michele Celebrano

Beilstein J. Nanotechnol. 2018, 9, 2306–2314, doi:10.3762/bjnano.9.215

• sizeable efficiency enhancement. First reported in individual silicon-on-insulator nanodisks [17] and soon after in a coupled nanodisk trimer configuration [18], the THG enhancement attained was up to 100 times higher than in a Si slab of the same thickness thanks to the exploitation of Mie-type resonances

Phosphorus monolayer doping (MLD) of silicon on insulator (SOI) substrates

• Noel Kennedy,
• Ray Duffy,
• Luke Eaton,
• Dan O’Connell,
• Scott Monaghan,
• Shane Garvey,
• James Connolly,
• Chris Hatem,
• Justin D. Holmes and
• Brenda Long

Beilstein J. Nanotechnol. 2018, 9, 2106–2113, doi:10.3762/bjnano.9.199

• Applied Materials, Gloucester, Massachusetts, USA CRANN@AMBER, Trinity College Dublin, Dublin 2, Ireland 10.3762/bjnano.9.199 Abstract This paper details the application of phosphorus monolayer doping of silicon on insulator substrates. There have been no previous publications dedicated to the topic of

• and will be problematic when attempting to reach doping levels achieved by rival techniques. Keywords: CMOS; doping; monolayer; silicon; silicon on insulator (SOI); Introduction Aggressive device scaling in the sub-20 nm region has resulted in a number of techniques that were previously essential

• them in the crystal structure. By contrast, Ye et al. have recently proposed a monolayer contact doping (MLCD) process without the need for a capping layer [13]. This paper will examine the application of phosphorus MLD to silicon on insulator (SOI) substrates with nanoscale dimensions (sub-66 nm

A differential Hall effect measurement method with sub-nanometre resolution for active dopant concentration profiling in ultrathin doped Si_1−xGe_x and Si layers

• Richard Daubriac,
• Emmanuel Scheid,
• Hiba Rizk,
• Richard Monflier,
• Sylvain Joblot,
• Rémi Beneyton,
• Pablo Acosta Alba,
• Sébastien Kerdilès and
• Filadelfo Cristiano

Beilstein J. Nanotechnol. 2018, 9, 1926–1939, doi:10.3762/bjnano.9.184

• mobility; contact resistance; differential Hall effect; dopant activation; fully depleted silicon on insulator (FDSOI); laser annealing; sub-nanometre resolution; Introduction The research efforts made throughout the last decades have made it possible to keep the momentum for a continuous miniaturization

• of electronics devices. For instance, the “bulk” planar transistor limitations have been overcome thanks to the transition towards more complex device architectures. These include enhanced planar architectures such as fully depleted silicon on insulator (FDSOI) [1] or 3D architectures ranging from

Effect of tetramethylammonium hydroxide/isopropyl alcohol wet etching on geometry and surface roughness of silicon nanowires fabricated by AFM lithography

• Siti Noorhaniah Yusoh and
• Khatijah Aisha Yaacob

Beilstein J. Nanotechnol. 2016, 7, 1461–1470, doi:10.3762/bjnano.7.138

• performance for many applications. Keywords: AFM lithography; isopropyl alcohol; silicon nanowires; tetramethylammonium hydroxide; wet etching; Introduction The fabrication of semiconductor devices on silicon-on-insulator (SOI) wafers has recently become popular. Devices necessary for meeting the

Review of nanostructured devices for thermoelectric applications

• Giovanni Pennelli

Beilstein J. Nanotechnol. 2014, 5, 1268–1284, doi:10.3762/bjnano.5.141

• nanowhiskers grow perpendicularly to the substrate. Exploiting the VLS-CVD technique, silicon nanowires have been grown between small suspended silicon masses, fabricated by micromachining techniques applied to silicon-on-insulator (SOI) substrates [86][87]. The silicon masses are maintained at different

• process, based on electron beam lithography, anisotropic silicon etching and stress-limited oxidation, is shown in the sketches of Figure 7. This process [91][92][93] has been developed on a silicon-on-insulator (SOI) substrate, <100> oriented, which is becoming largely employed in the semiconductor

Methods for rapid frequency-domain characterization of leakage currents in silicon nanowire-based field-effect transistors

• Tomi Roinila,
• Xiao Yu,
• Jarmo Verho,
• Tie Li,
• Pasi Kallio,
• Matti Vilkko,
• Anran Gao and
• Yuelin Wang

Beilstein J. Nanotechnol. 2014, 5, 964–972, doi:10.3762/bjnano.5.110

• from a SiNW FET. An n-type SiNW FET device was fabricated by using a silicon-on-insulator (SOI) wafer with a top-down method. A full description of the fabrication process is given in [25]. The structure of the device is schematically shown in Figure 4, where G, S, and D denote the gate, source, and

A highly pH-sensitive nanowire field-effect transistor based on silicon on insulator

• Denis E. Presnov,
• Sergey V. Amitonov,
• Pavel A. Krutitskii,
• Valentina V. Kolybasova,
• Igor A. Devyatov,
• Vladimir A. Krupenin and
• Igor I. Soloviev

Beilstein J. Nanotechnol. 2013, 4, 330–335, doi:10.3762/bjnano.4.38

• , Moscow 119991, Russia Keldysh Institute of Applied Mathematics, Moscow 125047, Russia 10.3762/bjnano.4.38 Abstract Background: An experimental and theoretical study of a silicon-nanowire field-effect transistor made of silicon on insulator by CMOS-compatible methods is presented. Results: A maximum

• approach does not yield to the one of sensors built in bottom-up approaches. This provides a good background for the development of CMOS-compatible probes with primary signal processing on-chip. Keywords: charge/field sensor; field-effect transistor; nanowire; pH sensor; silicon-on-insulator

• ; Introduction Over the past decade experimental and theoretical studies of semiconductor nanowire field-effect transistors (NW FET) made of silicon on insulator (SOI) have been of great interest to researchers. The large surface-to-volume ratio of the nanowire allows one to create extremely sensitive charge

Grating-assisted coupling to nanophotonic circuits in microcrystalline diamond thin films

• Patrik Rath,
• Svetlana Khasminskaya,
• Christoph Nebel,
• Christoph Wild and
• Wolfram H.P. Pernice

Beilstein J. Nanotechnol. 2013, 4, 300–305, doi:10.3762/bjnano.4.33

• index of 2.4, which is well suited for tightly confining light in subwavelength structures [16]. In order to prevent radiative loss into the surrounding medium, the diamond waveguiding layer needs to be surrounded by a material of lower refractive index. Here in analogy to silicon-on-insulator (SOI

• high-quality substrates, established fabrication routines, and a high refractive index [2][3][4]. For waveguiding in the telecommunications transmission window, thin silicon layers (surrounded by cladding material of lower refractive index) are required, which has led to the establishment of silicon-on

• -insulator (SOI) as a primary platform for nanophotonics [5][6]. However, silicon only provides a relatively small bandgap of 1.1 eV, which prevents waveguiding below 1100 nm. Furthermore, silicon is plagued be free-carrier absorption [7], which presents significant challenges for high-power applications and

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

• Farhad Larki,
• Arash Dehzangi,
• Alam Abedini,
• Ahmad Makarimi Abdullah,
• Elias Saion,
• Sabar D. Hutagalung,
• Mohd N. Hamidon and
• Jumiah Hassan

Beilstein J. Nanotechnol. 2012, 3, 817–823, doi:10.3762/bjnano.3.91

• .3.91 Abstract A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with

• microscope based lithography (SPL) via local anodic oxidation (LAO) was reported previously [7][8][9]. The experimental characteristics were also investigated and single-gate and double-gate structures were compared [10]. The principle of SPL on silicon-on-insulator (SOI) was described for the first time by