Effect of annealing treatments on CeO₂ grown on TiN and Si substrates by atomic layer deposition

• Silvia Vangelista,
• Rossella Piagge,
• Satu Ek and
• Alessio Lamperti

Beilstein J. Nanotechnol. 2018, 9, 890–899, doi:10.3762/bjnano.9.83

• when annealed at different temperatures and in reactive or inert gas atmospheres. A set of samples has been annealed at a temperature slightly above the growth temperature (300 °C), a value compatible with a back-end process flow typically used in microelectronics CMOS integration process, and in O2

• . Incidentally, such a high-temperature regime is typical of front-end CMOS processes, and could be of relevance to evaluate a possible CeO2 integration at this process step. Deposition of CeO2 thin films in previous studies has been achieved by using a variety of growth techniques, such as RF-magnetron

• severe limit in the integration of CeO2 films upon TiN in processes requiring exposure to temperatures above 600 °C after CeO2 deposition, as is required in many conventional CMOS processes. Because of such severe instability, we limited our considerations on this type of samples to this temperature. In

High-contrast and reversible scattering switching via hybrid metal-dielectric metasurfaces

• Jonathan Ward,
• Khosro Zangeneh Kamali,
• Lei Xu,
• Guoquan Zhang,
• Andrey E. Miroshnichenko and
• Mohsen Rahmani

Beilstein J. Nanotechnol. 2018, 9, 460–467, doi:10.3762/bjnano.9.44

• remarkable advantages in controlling optical responses [14][15][16][17][18]. All-dielectric, high refractive index metasurfaces are the second generation of metasurfaces [19]. Besides their CMOS compatibility and low optical losses compared with plasmonic metasurfaces, all-dielectric metasurfaces offer

Review: Electrostatically actuated nanobeam-based nanoelectromechanical switches – materials solutions and operational conditions

• Liga Jasulaneca,
• Jelena Kosmaca,
• Raimonds Meija,
• Jana Andzane and
• Donats Erts

Beilstein J. Nanotechnol. 2018, 9, 271–300, doi:10.3762/bjnano.9.29

• possibility to tune the Young’s modulus by changing an element size combined with facile integration with existing complementary metal oxide semiconductor (CMOS) devices, make metals attractive candidates for the use in NEM switches. However, metal-based NEM components with nanometre-scale dimensions are

• commercial CMOS technology [17]. 2T switches have been fabricated using the back end of line (BEOL) Cu layers of a commercial 65 nm CMOS technology. As-fabricated NEM switches showed jump-in voltages as low as 5.5 V, a good on/off ratio (103), and high miniaturisation level, surpassing other [17][23][49][114

• of NEM relay-only and CMOS–NEM hybrid circuits was demonstrated. Platinum cantilevers with thickness of ≈60–70 nm, length of ≈3.2–3.5 μm and gap of 100 nm, showed a jump-in voltage of 3.3 V in 3T configuration, and 5–6 V in the CMOS–NEM hybrid circuit [114]. Ruthenium also allows CMOS compatible

Dopant-stimulated growth of GaN nanotube-like nanostructures on Si(111) by molecular beam epitaxy

• Alexey D. Bolshakov,
• Alexey M. Mozharov,
• Georgiy A. Sapunov,
• Igor V. Shtrom,
• Nickolay V. Sibirev,
• Vladimir V. Fedorov,
• Evgeniy V. Ubyivovk,
• Maria Tchernycheva,
• George E. Cirlin and
• Ivan S. Mukhin

Beilstein J. Nanotechnol. 2018, 9, 146–154, doi:10.3762/bjnano.9.17

• efficiency of over 20% in such a simple SC [9]. The development of controllable methods of GaN nanostructure growth and doping on Si substrates opens up new possibilities for integration of III–V materials with established CMOS technology. The latter issue represents one of the bottlenecks of modern opto

Beyond Moore’s technologies: operation principles of a superconductor alternative

• Igor I. Soloviev,
• Nikolay V. Klenov,
• Sergey V. Bakurskiy,
• Mikhail Yu. Kupriyanov,
• Alexander L. Gudkov and
• Anatoli S. Sidorenko

Beilstein J. Nanotechnol. 2017, 8, 2689–2710, doi:10.3762/bjnano.8.269

• computing to be extraordinarily difficult, even if foreseeable advances in complementary metal-oxide-semiconductor (CMOS) technology are taken into account [10]. Low energy efficiency leads to high power consumption and also limits the clock frequency to 4–5 GHz. This frequency limit occurs due to

• Systems. The second part of the review is devoted to cryogenic memory. Four approaches are described: SQUID-based memory, hybrid Josephson–CMOS memory, Josephson magnetic random access memory (JMRAM), and orthogonal spin transfer magnetic random access memory (OST-MRAM). They are presented in historical

• comparison to conventional CMOS technology. Indeed, superconducting microstrip lines are able to transfer picosecond waveforms without distortions with a speed approaching the speed of light, for distances well exceeding typical chip sizes, and with low crosstalk [16]. This is the basis for fast long-range

Changes of the absorption cross section of Si nanocrystals with temperature and distance

• Michael Greben,
• Petro Khoroshyy,
• Sebastian Gutsch,
• Daniel Hiller,
• Margit Zacharias and
• Jan Valenta

Beilstein J. Nanotechnol. 2017, 8, 2315–2323, doi:10.3762/bjnano.8.231

• silicon, which reveals all advantages of the quantum confinement effect [1], is a promising candidate for the development of a new generation of Si photovoltaic and photonic devices [2]. SiO2-embedded silicon nanocrystals (Si NCs) can be relatively easy integrated into current CMOS technology. In

Ta₂N₃ nanocrystals grown in Al₂O₃ thin layers

• Krešimir Salamon,
• Maja Buljan,
• Iva Šarić,
• Mladen Petravić and
• Sigrid Bernstorff

Beilstein J. Nanotechnol. 2017, 8, 2162–2170, doi:10.3762/bjnano.8.215

• alternative plasmonic materials includes the transition-metal nitrides such as TiN, ZrN, TaN or HfN [11][12][13]. Their advantages are compatibility with the silicon CMOS technology and physical properties suitable for harsh environments (high melting point, chemical stability) [14]. In addition, most of

The integration of graphene into microelectronic devices

• Guenther Ruhl,
• Sebastian Wittmann,
• Matthias Koenig and
• Daniel Neumaier

Beilstein J. Nanotechnol. 2017, 8, 1056–1064, doi:10.3762/bjnano.8.107

• aspects of the integration of graphene into complementary metal-oxide semiconductor (CMOS) compatible electronic devices. Review 1 Deposition of graphene Graphene films can synthesized in numerous ways, such as mechanical exfoliation, liquid-phase exfoliation, assembly of tailored precursor molecules

• from the CVD process, but also Fe is found in remarkable amounts. Several cleaning processes have been evaluated, but no substantial contamination removal could be achieved [39]. These metal contamination levels do not only lead to difficult integration into CMOS process lines (the typical upper

• . Both mechanisms result an increased contact resistance. Besides through choosing an appropriate metal, the contact resistance can be improved by thorough interface engineering [54] and applying an electrical field under the contacts to adjust the Fermi energy [55][56]. With respect to CMOS integration

CVD transfer-free graphene for sensing applications

• Chiara Schiattarella,
• Sten Vollebregt,
• Tiziana Polichetti,
• Brigida Alfano,
• Ettore Massera,
• Maria Lucia Miglietta,
• Girolamo Di Francia and
• Pasqualina Maria Sarro

Beilstein J. Nanotechnol. 2017, 8, 1015–1022, doi:10.3762/bjnano.8.102

• surface area. A study on graphene that was synthetized by means of a novel transfer-free fabrication approach and is employed as sensing material is herein presented. Multilayer graphene was deposited by chemical vapour deposition (CVD) mediated by CMOS-compatible Mo. The utilized technique takes

• straightforward integration in electronic devices. Keywords: ammonia; chemiresistors; CMOS-compatible process; graphene; nitrogen dioxide; transfer-free growth; Introduction Due to its extraordinary electronic, chemical, mechanical, thermal and optical properties, graphene has been defined as the “wonder

• . In a CMOS-compatible process, all these devices could be directly fabricated on the same chip at micrometre-size. It is finally worth mentioning that, once proven the reliability of this process, it paves the way for the creation of a sensor array, able to provide selective responses towards the

Copper atomic-scale transistors

• Fangqing Xie,
• Maryna N. Kavalenka,
• Moritz Röger,
• Daniel Albrecht,
• Hendrik Hölscher,
• Jürgen Leuthold and
• Thomas Schimmel

Beilstein J. Nanotechnol. 2017, 8, 530–538, doi:10.3762/bjnano.8.57

• V) of the three most promising approaches, namely multigate transistors, tunnel field-effect transistors, and germanium nanodevices [59][60][61][62]. The dynamic power dissipation of the CMOS devices is proportional to the square of drain supply voltage (VDD) [58]. The copper atomic-scale

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring

• Niina Halonen,
• Joni Kilpijärvi,
• Maciej Sobocinski,
• Timir Datta-Chaudhuri,
• Antti Hassinen,
• Someshekar B. Prakash,
• Peter Möller,
• Pamela Abshire,
• Sakari Kellokumpu and
• Anita Lloyd Spetz

Beilstein J. Nanotechnol. 2016, 7, 1871–1877, doi:10.3762/bjnano.7.179

• are miniaturized analytical tools that combine sophisticated microfluidics with sensing or analysis [12][13][14]. Lab-on-CMOS (LoCMOS) is an emerging class of LoC that combines LoC with integrated circuits (ICs). LOCs are often used for analyzing chemical or biological samples. However, when the wet

• was probably made too hastily based on our current knowledge of the LTCC material. We recently reported on an LTCC package that was flip-chip bonded to a complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) chip to form a LoCMOS system [23]. It was designed with a CMOS chip for

• The capacitance sensor chips (3 × 3 mm2) were fabricated in a commercial 2-poly, 3-metal, 0.5 µm CMOS process, as demonstrated in Figure 1b and c. The fully differential sensor chip was designed for measuring capacitance in the ±25 fF range. Each sensor contained two interdigitated capacitors, one

Nanostructured germanium deposited on heated substrates with enhanced photoelectric properties

• Ionel Stavarache,
• Valentin Adrian Maraloiu,
• Petronela Prepelita and
• Gheorghe Iordache

Beilstein J. Nanotechnol. 2016, 7, 1492–1500, doi:10.3762/bjnano.7.142

• , good process compatibility with the well-developed CMOS technology, and the extension of the photosensitivity range to the near-infrared (NIR) are the properties that make devices based on Ge nanoparticles (Ge-nps) promising candidates to substitute or to improve the conventional Si-based devices [1][2

• photodetector test structure, current density versus voltage (J–V) measurements, in dark and under integral light illumination were recorded in CMOS configuration. In the drawing presented in Figure 3, the measurement set-up and sample structure are described schematically. The active area of the test

Effect of tetramethylammonium hydroxide/isopropyl alcohol wet etching on geometry and surface roughness of silicon nanowires fabricated by AFM lithography

• Siti Noorhaniah Yusoh and
• Khatijah Aisha Yaacob

Beilstein J. Nanotechnol. 2016, 7, 1461–1470, doi:10.3762/bjnano.7.138

• potassium hydroxide solution that has become a popular anisotropic etchant because of its good etching performance and lack of toxicity. However, KOH is not CMOS compatible because of the mobile K+ ion contamination [16]. By contrast, TMAH has attracted the interest of researchers because of its simple

• handling and CMOS compatibility. According to Merlos et al. [16], a smooth surface, free of hillocks can be obtained by using TMAH as an etchant with a concentration greater than 25 wt %. Hutagalung and Lew [17] used 25 wt % of TMAH at 65 °C for 30 s to remove unmasked silicon layers. Then, an improvement

Photocurrent generation in carbon nanotube/cubic-phase HfO₂ nanoparticle hybrid nanocomposites

• Protima Rauwel,
• Augustinas Galeckas,
• Martin Salumaa,
• Frédérique Ducroquet and
• Erwan Rauwel

Beilstein J. Nanotechnol. 2016, 7, 1075–1085, doi:10.3762/bjnano.7.101

• gap of 5.7 eV [14][15]. HfO2 has already been integrated in numerous technologies and has been chosen for the replacement of Si-based gate oxides in advanced complementary metal-oxide semiconductors (CMOS) [16]. Many efforts have been made towards the stabilization of the cubic phase of HfO2 due to

Rigid multipodal platforms for metal surfaces

• Michal Valášek,
• Marcin Lindner and
• Marcel Mayor

Beilstein J. Nanotechnol. 2016, 7, 374–405, doi:10.3762/bjnano.7.34

• formation [63][70]. Although thiol monolayers have received considerable interest in the scientific community, the stability of these SAMs and the poor tolerability of Au in CMOS technology, considerably reduces the application potential. In particular, these organic films exhibit only moderate stability

Synthesis and applications of carbon nanomaterials for energy generation and storage

• Marco Notarianni,
• Jinzhang Liu,
• Kristy Vernon and
• Nunzio Motta

Beilstein J. Nanotechnol. 2016, 7, 149–196, doi:10.3762/bjnano.7.17

Possibilities and limitations of advanced transmission electron microscopy for carbon-based nanomaterials

• Xiaoxing Ke,
• Carla Bittencourt and
• Gustaaf Van Tendeloo

Beilstein J. Nanotechnol. 2015, 6, 1541–1557, doi:10.3762/bjnano.6.158

• ratio. A recent development in an advanced high-resolution fast-detection camera (K2-IS camera from Gatan Inc.) has made a significant improvement in both sensitivity and resolution by the elimination of the traditional scintillation process and the capture of electrons directly on a CMOS (complimentary

A scanning probe microscope for magnetoresistive cantilevers utilizing a nested scanner design for large-area scans

• Tobias Meier,
• Alexander Förste,
• Ali Tavassolizadeh,
• Karsten Rott,
• Dirk Meyners,
• Roland Gröger,
• Günter Reiss,
• Eckhard Quandt,
• Thomas Schimmel and
• Hendrik Hölscher

Beilstein J. Nanotechnol. 2015, 6, 451–461, doi:10.3762/bjnano.6.46

• such structures with a special large-area scanning AFM allows for inspection of a wide field of the chip architecture within one scan. Figure 4b shows a portion of the die surface of a UV-erasable CMOS EPROM memory chip (Type 27C256). The image size is 500 × 500 μm2 imaged with a resolution of 1024

• microscope image with the AFM topography of an optical grating structure with a 256 × 256 μm2 grating periodicity. b) Large-area AFM topography image of a part of a UV-erasable CMOS EPROM memory chip with a scan size of 500 × 500 μm2. Despite the large step heights of 2 μm, there no artefacts are visible, no

Nanoporous Ge thin film production combining Ge sputtering and dopant implantation

• Jacques Perrin Toinin,
• Alain Portavoce,
• Khalid Hoummada,
• Michaël Texier,
• Maxime Bertoglio,
• Sandrine Bernardini,
• Marco Abbarchi and
• Lee Chow

Beilstein J. Nanotechnol. 2015, 6, 336–342, doi:10.3762/bjnano.6.32

• is compatible with complementary metal oxide semiconductor (CMOS) technology, the production of porous Ge thin films could be used for integration of optoelectronic devices in Si microelectronic technology. The production of porous Ge can be performed using several techniques such as anodization and

• diffusion mechanism of Se and Te atoms [41]. Conclusion The fabrication of highly-doped, porous Ge thin films (which are of high potential use for optoelectronic device fabrication) was successfully achieved using experimental techniques compatible with Si CMOS technology. High-dose (>1015 atoms/cm2) dopant

Bright photoluminescence from ordered arrays of SiGe nanowires grown on Si(111)

• D. J. Lockwood,
• N. L. Rowell,
• A. Benkouider,
• A. Ronda,
• L. Favre and
• I. Berbezier

Beilstein J. Nanotechnol. 2014, 5, 2498–2504, doi:10.3762/bjnano.5.259

• have been demonstrated for specific core/shell NW configurations with an ultimate control over the NW shape, aspect ratio and radial multishell composition [7]. A major asset of Si/Ge core/shell [8] and axial [9] NW heterostructures is also their ease of integration in CMOS technology, which allows the

• over those produced by other vapor-solid-solid growth methods and that could be useful for applications in optoelectronic nanodevices. However, their mass production in current CMOS production lines would be problematic. Schematic representation of the process steps: (a) formation of SiO2 (5 nm thick

Electrical contacts to individual SWCNTs: A review

• Wei Liu,
• Christofer Hierold and
• Miroslav Haluska

Beilstein J. Nanotechnol. 2014, 5, 2202–2215, doi:10.3762/bjnano.5.229

• a process flow for wafer-scale CNFET fabrication, which is compatible with the current CMOS fabrication processes, but the SWCNTs require transfer to a target wafer. The physically and chemically induced impacts on the SWCNT properties which occur during the SWCNT transfer process must be further

Advances in NO₂ sensing with individual single-walled carbon nanotube transistors

• Kiran Chikkadi,
• Matthias Muoth,
• Cosmin Roman,
• Miroslav Haluska and
• Christofer Hierold

Beilstein J. Nanotechnol. 2014, 5, 2179–2191, doi:10.3762/bjnano.5.227

• channel and overlaps the source and drain contacts. Top-gate architectures, which have a closer resemblance to CMOS architectures, are less common for gas sensors due to the need for an exposed channel. Side-gate configurations are not typically used due to their poor gate coupling. Variants of this basic

Silicon and germanium nanocrystals: properties and characterization

• Ivana Capan,
• Alexandra Carvalho and
• José Coutinho

Beilstein J. Nanotechnol. 2014, 5, 1787–1794, doi:10.3762/bjnano.5.189

• formation and the formation of the sub-oxide interface states [23]. As ion implantation is unavoidable for CMOS technology today, it is desirable to use it not only for the fabrication of NCs but for the doping of NCs as well. Over the past decade, phosphorus-and erbium-doped Si NCs have attracted a great

Sublattice asymmetry of impurity doping in graphene: A review

• James A. Lawlor and
• Mauro S. Ferreira

Beilstein J. Nanotechnol. 2014, 5, 1210–1217, doi:10.3762/bjnano.5.133

• of over 8%, where impurities are all on the same sublattice, will produce a band gap of around 550 meV far surpassing the minimum required for a CMOS [14][36] and finding that the band gap scales with concentration to the power 3/4, as shown in Figure 3. Even with a 4:1 doping ratio between

A highly pH-sensitive nanowire field-effect transistor based on silicon on insulator

• Denis E. Presnov,
• Sergey V. Amitonov,
• Pavel A. Krutitskii,
• Valentina V. Kolybasova,
• Igor A. Devyatov,
• Vladimir A. Krupenin and
• Igor I. Soloviev

Beilstein J. Nanotechnol. 2013, 4, 330–335, doi:10.3762/bjnano.4.38

• , Moscow 119991, Russia Keldysh Institute of Applied Mathematics, Moscow 125047, Russia 10.3762/bjnano.4.38 Abstract Background: An experimental and theoretical study of a silicon-nanowire field-effect transistor made of silicon on insulator by CMOS-compatible methods is presented. Results: A maximum

• Nernstian sensitivity to pH change of 59 mV/pH was obtained experimentally. The maximum charge sensitivity of the sensor was estimated to be on the order of a thousandth of the electron charge in subthreshold mode. Conclusion: The sensitivity obtained for our sensor built in the CMOS-compatible top-down

• approach does not yield to the one of sensors built in bottom-up approaches. This provides a good background for the development of CMOS-compatible probes with primary signal processing on-chip. Keywords: charge/field sensor; field-effect transistor; nanowire; pH sensor; silicon-on-insulator