Scaling towards the sub-10nm technology node involves the development of new materials (e.g., Ge, III-V, graphene) and new device architectures (e.g., FinFETs, GAA-FETs, thin-film FETs). The more complex underlying physics at this scale and the exponential increase of technological options has led to growing integration challenges, and hence, to a growing need for technology computer aided design (TCAD) simulations. Furthermore, the development of TCAD tools is intimately linked with the development of advanced metrology solutions to calibrate them. Thus, this collection of articles aims to present recent progresses in advanced metrology and innovative solutions necessitating physical simulations to replace experiments and facilitate the rapid development of new devices. Additionally, current integration challenges for such new devices are highlighted. Topics include:

• 2D/3D dopant and carrier profiling techniques with nanometer resolution
• Metrology techniques that provide information about sub-10 nm structures with sufficient depth and 2D/3D resolution (e.g., electrical AFM, atom probe or electron holography, TOF-SIMS, s-SNOM, TEM)
• New high-mobility channel materials (III-V and Ge)
• Thin body (ultra-thin SOI, double or tri-gate multigates, nanowires) and vertical gate-all-around device architectures
• Novel contact and doping techniques for low-access resistance
• Physical simulations (ab-initio, molecular dynamics, lattice/on-lattice kinetic Monte Carlo, partial differential equations) for the development of new sub-10 nm devices